The present invention relates to a system and method for protecting integrated circuits from electrostatic discharge (ESD) and, more particularly, to the firing of a silicon controlled rectifier (SCR), operative to provide a safe discharge path for the ESD current, via a low-voltage triggering mechanism. High speed input/output (I/O) buffers transmitting signals at data rates higher than 5 Gbps incorporate semiconductor devices having oxides as thin as 20-30 Angstrom. These oxides must be protected from ESD. In order not to diminish the electronic performance of these I/O buffers the ESD protection must introduce very little parasitic capacitance or serial resistance. The present invention presents an ESD protection solution that meets these requirements by utilizing a current-triggered low turn-on voltage parasitic SCR intrinsic to the semiconductor device.
Various attempts have been made to provide solutions for low-capacitance ESD protection using an SCR. U.S. Pat. No. 6,268,992 to Lee et al. describes a displacement current trigger SCR that uses AC currents that charge a capacitor for triggering the parasitic SCR. This solution introduces additional capacitance to the pad.
U.S. Pat. No. 5,400,202 to Metz et al. describes a trigger circuit having an NMOS triggering transistor for activating the SCR. The NMOS transistor itself may be harmed by the ESD event; in addition, the NMOS transistor introduces leakage current and also introduces voltage stress limitations.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system and method for protecting integrated circuits from ESD without introducing additional capacitance to I/O pads or leakage currents, and with greater tolerance for voltage stress.